A) Field
The present invention relates to a compound semiconductor device and its manufacture method, and more particularly to a compound semiconductor device such as a high electron mobility transistor (HEMT) using an InP substrate.
B) Description of the Related Art
One type of HEMT using an InP substrate has a structure that after a buffer layer, a channel (electron transfer) layer and a carrier (electron) supply layer are laminated on an InP substrate, a cap layer for contact is formed, the cap layer under a gate electrode is removed, and a T type gate electrode is formed on the carrier supply layer. In order to retain adhesion between the compound semiconductor layer surface and a resist layer, it is desired to form an insulating film on the compound semiconductor surface.
JP-A-HEI-6-232179 discloses a method and structure that an insulating film is laminated on a cap layer, an opening is formed through the insulating layer, and that the cap layer is wet-etched via the opening to form a gate electrode.
The structure shown in FIG. 5A is formed by manufacture processes illustrated in FIGS. 5B to 5E.
As shown in FIG. 5B, by molecular beam epitaxy (MBE) or organic metal vapor phase epitaxy (OMVPE), on a semi-insulating InP substrate 110, a buffer layer 111 of non-doped InP or InAlAs lattice-matching with InP is grown to a thickness of about 300 nm, a channel layer 112 of InGaAs is grown on the buffer layer 111 to a thickness of about 15 nm, an electron supply layer 113 of In0.52Al0.48As having an electron concentration of 5×1018/cm3 is grown on the channel layer 112 to a thickness of 40 nm, and a cap layer 114 of In0.53Ga0.47As having an electron concentration of 5×1018/cm3 is grown on the electron supply layer 113 to a thickness of 10 nm. The channel layer 112 may be made of InP.
As shown in FIG. 5C, drain/source ohmic electrodes 115 and 116 are formed in predetermined areas on the cap layer 114 by vapor deposition, and an alloying process is executed to form high concentration n-type regions under the ohmic electrodes 115 and 116. Next, by plasma CVD, an SiN insulating film 117 is deposited to a thickness of about 50 to 100 nm. This insulating film may be made of insulating material capable of being formed at a lower temperature than SiN, such as SiO2 and SiON.
As shown in FIG. 5D, a photoresist mask FA having an opening is formed by photolithography, and by using the photoresist film FA as an etching mask, the insulating film 117 is etched and removed from the region where an opening A1 is to be formed. This opening A1 functions as a mask when recess-etching to be described later is performed, and defines a channel length and a channel width of the gate electrode. After the opening A1 is formed, the photoresist film FA is removed.
As shown in FIG. 5E, a photoresist film FB is formed by photolithography, having an opening B1 being inclusive of the opening A1 and broader than the opening A1. After the photoresist film FB is formed, by using the insulating film 117 as a mask, the cap layer 114 is recess-etched to form a recess in the cap layer 114, the recess being broader than the opening A1 of the insulating film 117. This recess-etching may use etchant of aqueous solution of phosphoric acid and aqueous solution of hydrogen peroxide. A recess structure is also formed in the electron supply layer 113.
Next, Ti/Pt/Au are sequentially vapor-deposited to thicknesses of 50/50/500 nm, respectively. The unnecessary photoresist FB is removed by lift-off to form a Schottky gate electrode 118 shown in FIG. 5A. The Schottky gate electrode 118 is formed in a rectangular shape along the opening A1 of the insulating film 117, and does not contact the cap layer 114 although it contacts the electron supply layer 113. The opening A1 is hermetically sealed by the Schottky gate electrode 118 and an inner gap of the recess structure is shielded perfectly from an external atmosphere.
According to the structure and manufacture method illustrated in FIGS. 5A to 5E, the SiN film used as a mask for recess-etching regulates a layout of the gate electrode. The gate electrode cannot be made nearer to the side edge of the cap layer than the opening position of the SiN film. The recess structure is symmetrical relative to the gate electrode, and a drain offset structure cannot be realized, which structure lowers the source resistance and improves a drain breakdown voltage by making the gate electrode near to the source electrode and remoter from the drain electrode. If a resist pattern is formed directly on the cap layer, adhesion of resist is bad and wet-etching liquid permeates into the interface. Wet-etching cannot be performed at a high precision.
International Publication WO 03/067764 proposes that a dummy pattern of phosphosilicate glass (PSG) or the like is formed on a cap layer, an SiN film is deposited on the dummy pattern, an opening is formed through the SiN film, having a shape that a gate electrode is to be accommodated and reaching the cap layer at asymmetric positions relative to the source and drain, the dummy pattern is etched via the opening, and the cap layer under the area from which the dummy pattern was removed is etched to thereby realize the drain offset structure. Similar to JP-A-HEI-6-232179, the SiN film of a hood shape exists above the cap layer, and the gate electrode contacts the SiN film. Although the drain offset structure can be realized, the layout or disposal of the gate electrode is limited by the hood structure of the SiN film, and parasitic capacitance is formed between the gate electrode and the SiN film of the hood shape.